Surface Stress Evolution in Through Silicon Via Wafer During a Backside Thinning Process Academic Article

authors

• Fang, Gwo-Ping
• Liang, Hong

published proceedings

• IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING

author list (cited authors)

• Jiang, B., Chen, Y., Fang, A., Liu, B., Liu, Y., Liang, H., & Lu, X.

citation count

• 2

complete list of authors

• Jiang, Bocheng||Chen, Yan||Fang, Alex||Liu, Bingtong||Liu, Yuhong||Liang, Hong||Lu, Xinchun

publication date

• November 2019

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• IEEE Transactions on Semiconductor Manufacturing  Journal

keywords

• Chemical Mechanical Polishing
• Lapping
• Residual Stresses
• Silicon
• Surface Cracks
• Surface Stress
• Surface Treatment
• Through Silicon Via
• Through-silicon Vias
• Wafer Backside Thinning

Digital Object Identifier (DOI)

• 10.1109/TSM.2019.2937004

start page

• 589

end page

• 595

volume

• 32

issue

• 4

URL

• http://dx.doi.org/10.1109/tsm.2019.2937004