A 27.7 fJ/conv-step 500 MS/s 12-Bit Pipelined ADC Employing a Sub-ADC Forecasting Technique and Low-Power Class AB Slew Boosted Amplifiers
Academic Article
Overview
Research
Identity
Additional Document Info
Other
View All
Overview
abstract
2004-2012 IEEE. This paper presents a 12-bit 500 MS/s pipelined ADC fabricated in the 40 nm TSMC technology, which aims to reduce the power consumption associated with residue amplifiers and comparator cells. ADC architecture employs amplifiers with minimum transconductance requirements while considering the minimum unit capacitance value to maintain matching capacitor requirements for the target ADC specifications. The power efficient operational amplifiers are equipped with a Class C slew-rate boosting circuit that achieves a high slew-rate while static power is significantly saved. In addition, a forecasting technique in the sub-ADC is proposed, which reduces the number of active comparators during the sub-ADC's conversion phase. The sign of the incoming signal is detected, and then the number of active comparators in each conversion cycle reduces by half, which leads to a more than 46% dynamic power savings from the sub-ADCs. The ADC achieves an SNDR/SFDR of 65.9/82.3 dB at low input frequencies and 64.1/75.5 dB near Nyquist frequency while running at 500 MS/s. The pipelined ADC prototype occupies an active area of 0.9 mm2 and consumes 18.16 mW from a 1.1 V supply, resulting in a figure of merit (FOM) of 22.4 and a 27.7 fJ/conversion-step at low-frequency and Nyquist frequency, respectively.
