Upper and lower bounds for one-write multivalued regular registers Conference Paper uri icon


  • 1991 IEEE. This paper presents an algorithm for implementing a k-ary regular register (the logical register) using k(k-1)/2 binary regular registers (the physical registers) that requires only one physical write per logical write. The algorithm is simple to describe and depends on properties of paths in a related graph. Two lower bounds on the number of registers required by one-write implementations are given. The first lower bound holds for a restricted class of implementations and implies that the authors' algorithm is optimal for this class. The second lower bound, 2k-1-(log k), holds for a more general class of algorithms. Both lower bounds improve on the best previously known lower bound, which was k. Their second lower bound uses a general result for transforming a one-write algorithm into another one-write algorithm for fewer logical values using fewer physical registers. They show that for any one-write algorithm, there is no advantage, in terms of number of physical registers, to be gained if readers write, or if different readers follow different protocols, or if a reader's protocol depends on its history. Furthermore, for the second class of algorithms, there is also no advantage to be gained if the reader reads some physical registers more than once. These results are shown using transformation techniques similar to the one mentioned previously.

name of conference

  • Third IEEE Symposium on Parallel and Distributed Processing

published proceedings

  • Proceedings of the Third IEEE Symposium on Parallel and Distributed Processing

author list (cited authors)

  • Chaudhuri, S., Kosa, M. J., & Welch, J. L.

publication date

  • January 1, 1991 11:11 AM