Fast algorithms for image labeling on a reconfigurable network of processors Conference Paper uri icon

abstract

  • 1993 IEEE. This paper presents constant-time algorithms for labeling the connected components of images on a network of processors with a wide reconfigurable bus. The algorithms are based on a processor indexing scheme which employs constant-weight codes. The use of such codes enables identifying a single representative processor for each component in a constant number of steps. The proposed algorithms can label an NN image or an N-vertex graph in O(1) time using Theta (N2) processors, which is optimal. Furthermore, the proposed techniques lead to O(log N/log log N)-time labeling algorithms on a network of N2 processors with a reconfigurable bus of width O(log N) bits.

name of conference

  • [1993] Seventh International Parallel Processing Symposium

published proceedings

  • [1993] Proceedings Seventh International Parallel Processing Symposium

author list (cited authors)

  • Alnuweiri, H. M.

publication date

  • January 1, 1993 11:11 AM