Managing the bottlenecks of a parallel Gauss-Seidel algorithm for power flow analysis Conference Paper

abstract

• 1993 IEEE. In our earlier papers, the parallelization and implementations of Gauss-Seidel (G-S) algorrthms for power flow analysis have been investigated on a Sequent flnlnnce ahared memory (SM) machine. In this paper, we generalize the idea to more genernl computer architectures and demonstrate how to eflectiuely increase the speedup upper bounds of G-S algorithms by properly managing the bottlenecks.

name of conference

• [1993] Proceedings Seventh International Parallel Processing Symposium

authors

• Huang, Garng

published proceedings

• [1993] Proceedings Seventh International Parallel Processing Symposium

author list (cited authors)

• Huang, G., & Ongsakul, W.

citation count

• 3

complete list of authors

• Huang, G||Ongsakul, W

publication date

• January 1993

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

Digital Object Identifier (DOI)

• 10.1109/ipps.1993.262781

International Standard Book Number (ISBN) 10

• 0818634421

International Standard Book Number (ISBN) 13

• 9780818634420

start page

• 787

end page

• 791

URL

• http://dx.doi.org/10.1109/ipps.1993.262781