A 13-bit Noise Shaping SAR-ADC with Dual-Polarity Digital Calibration. Academic Article uri icon


  • We present a new noise shaping method and a dual polarity calibration technique suited for successive approximation register type analog to digital converters (SAR-ADC). Noise is pushed to higher frequencies with the noise shaping by adding a switched capacitor. The SAR capacitor array mismatch has been compensated by the dual-polarity digital calibration with minimum circuit overhead. A proof-of-concept prototype SAR-ADC using the proposed techniques has been fabricated in a 0.5-m standard CMOS technology. It achieves 67.7 dB SNDR at 62.5 kHz sampling frequency, while consuming 38.3W power with 1.8 V supply.

published proceedings

  • Analog Integr Circuits Signal Process

altmetric score

  • 6

author list (cited authors)

  • Park, H., & Ghovanloo, M.

citation count

  • 5

complete list of authors

  • Park, Hangue||Ghovanloo, Maysam

publication date

  • June 2013