A multiple floating point coprocessor architecture Conference Paper uri icon

abstract

  • 1990 IEEE Computer Society. All rights reserved. General purpose microprocessor based computers usually speed their arithmetic processing performance by using a floating point co-processor. Because adding more co-processors represents neither a technological nor a cost problem we investigated a system based on a MIPS R2000 [2] and 4 floating point units. In this paper we show a block diagram of such an implementation and how two important scientific operations can be accelerated using a single unmodified data bus. A large percentage of the engineering applications are solved with the help of linear algebra methods like BLAS3 [4] algorithms; It is precisely for these primitives that the proposed architecture brings significant performance gains. The first operation described will be a matrix multiplication algorithm, its timing diagram and some results. Next a polynomial evaluation technique will be examined. Finally we show how to use the same ideas with various other microprocessors.

name of conference

  • [1990] 23rd Annual Workshop and Symposium@m_MICRO 23: Microprogramming and Microarchitecture

published proceedings

  • [1990] Proceedings of the 23rd Annual Workshop and Symposium@m_MICRO 23: Microprogramming and Microarchitecture

author list (cited authors)

  • Rauchwerger, L., & Farmwald, P. M.

publication date

  • January 1, 1990 11:11 AM