Symmetric Block-wise Concatenated BCH Codes for NAND Flash Memories Academic Article uri icon

abstract

  • © 1972-2012 IEEE. This paper introduces a high rate error-correcting coding scheme called symmetric block-wise concatenated Bose-Chaudhuri-Hocquenghem (symmetric BC-BCH) codes tailored for storage devices with hard-decision outputs, e.g., storage devices based on NAND flash memory. It will be shown that a careful integration of the symmetry and 2-D block-wise concatenation is especially beneficial to achieve improvements of error-rate performance when an iterative hard-decision-based decoding (IHDD) is assumed. The claim is substantiated by proving that the proposed symmetric concatenation is optimal in terms of error-rate performance in the low error-rate regime over other 2-D block-wise concatenations. Besides, this paper proposes a novel way to design constituent codes, which enables us to enjoy advantages of primitive BCH codes and to efficiently break stopping sets associated with the IHDD in the low error-rate regime. We consider error-control systems made up of a symmetric BC-BCH code, the IHDD, and simple auxiliary decoders specifically targeting to break stopping sets caused in the IHDD. It will be shown that the auxiliary decoders significantly improve error-rate performance at a negligible amount of extra complexity. Performance comparisons are also carried out between error-control systems with the proposed and other coding schemes such as BCH codes, quasi-primitive BC-BCH codes, and low-density parity-check codes.

published proceedings

  • IEEE Transactions on Communications

altmetric score

  • 3

author list (cited authors)

  • Kim, D., Narayanan, K., & Ha, J.

citation count

  • 7

complete list of authors

  • Kim, Daesung||Narayanan, Krishna||Ha, Jeongseok

publication date

  • May 2018