IEEE P1581 - Getting More Board Test Out of Boundary Scan Conference Paper

abstract

• IEEE P1581 has undergone significant improvement since its introduction. This paper explains the choice of simple, low overhead solutions the proposed standard provides in overcoming one of Boundary Scan's greatest bottlenecks: test of complex memory devices. Design for Testability guidelines are provided to allow board designers and test engineers to take full advantage of this new test technique. 2006 IEEE.

name of conference

• 2006 IEEE International Test Conference

authors

• Russell, B. Don

published proceedings

• International Test Conference 1999 Proceedings (IEEE Cat No99CH37034)

author list (cited authors)

• Ehrenberg, H., Russell, B., & Van Treuren, B.

citation count

• 5

complete list of authors

• Ehrenberg, Heiko||Russell, Bob||Van Treuren, Bradford

publication date

• January 2006

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• International Test Conference  Journal

Digital Object Identifier (DOI)

• 10.1109/test.2006.297707

International Standard Book Number (ISBN) 10

• 1424402921

International Standard Book Number (ISBN) 13

• 9781424402922

start page

• 1

end page

• 10

URL

• http://dx.doi.org/10.1109/test.2006.297707