IEEE P1581 Getting More Board Test Out of Boundary Scan Conference Paper uri icon

abstract

  • IEEE P1581 has undergone significant improvement since its introduction. This paper explains the choice of simple, low overhead solutions the proposed standard provides in overcoming one of Boundary Scan's greatest bottlenecks: test of complex memory devices. Design for Testability guidelines are provided to allow board designers and test engineers to take full advantage of this new test technique. 2006 IEEE.

name of conference

  • 2006 IEEE International Test Conference

published proceedings

  • 2006 IEEE International Test Conference

author list (cited authors)

  • Ehrenberg, H., Russell, B., & Treuren, B.

publication date

  • January 1, 2006 11:11 AM

publisher