A 56 Gb/s PAM4 Receiver with Low-Overhead Threshold and Edge-Based DFE FIR and IIR-Tap Adaptation in 65nm CMOS

2018 IEEE. A PAM4 quarter-rate receiver employs a singlestage CTLE and a DFE with 1 FIR and 1 IIR-taps to efficiently compensate for channel loss. In addition to the per-slice main 3 data samplers, an error sampler is utilized for background threshold control and an edge-based sampler performs both PLL-based CDR phase detection and generates information for background DFE tap adaptation. Fabricated in GP 65nm CMOS, the 56Gb/s receiver achieves 4.63mW/Gb/s and compensates for up to 20.8dB loss when operated with a 2-tap FFE transmitter.

Roshan-Zamir, A., Iwai, T., Fan, Y., Kumar, A., Yang, H., Sledjeski, L., ... Palermo, S.

Roshan-Zamir, Ashkan||Iwai, Takayuki||Fan, Yang-Hang||Kumar, Ankur||Yang, Hae-Woong||Sledjeski, Lee||Hamilton, John||Chandramouli, Soumya||Aude, Arlo||Palermo, Samuel

A 56 Gb/s PAM4 Receiver with Low-Overhead Threshold and Edge-Based DFE FIR and IIR-Tap Adaptation in 65nm CMOS Conference Paper