A 50 Gb/s PAM-4 VCSEL Transmitter With 2.5-Tap Nonlinear Equalization in 65-nm CMOS

© 1989-2012 IEEE. Utilizing four-level pulse-amplitude modulation (PAM-4) with vertical-cavity surface emitting lasers (VCSELs) is challenging due to device nonlinearity and bandwidth limitations. This letter presents a VCSEL-based PAM-4 transmitter that employs a 2.5-tap nonlinear equalizer to compensate for these issues. The transmitter utilizes lookup-table control of a current-mode digital-to-analog converter (DAC) output stage to enable independent equalization coefficients for different PAM-4 symbol transitions. Utilizing half pre-cursor (MSB only), one main, and one post-cursor taps provides a good balance between circuit complexity and performance. Equalization resolution is increased by segmenting the output stage into a 2-bit symbol DAC and a fine 3-bit equalization DAC. Fabricated in GP 65-nm CMOS, the serializing transmitter operates at 50 Gb/s with 3-dBm optical modulation amplitude (OMA) when driving an 11-GHz VCSEL and achieves 5.12 pJ/bit power efficiency.

Tyagi, A., Iwai, T., Yu, K., Wang, B., Sorin, W., Mathai, S., Tan, M., & Palermo, S.

A 50 Gb/s PAM-4 VCSEL Transmitter With 2.5-Tap Nonlinear Equalization in 65-nm CMOS Academic Article