Synchronous bus arbitration with constant logic per module
Conference Paper
Overview
Identity
Additional Document Info
Other
View All
Overview
abstract
A novel technique for distributed synchronous bus arbitration is presented in this paper. The proposed scheme is based on two orthogonal arbitration functions, one that employs bounded-weight binary codes, and another that employs unitary codes. This scheme trades off bus-width with arbitration-time and arbitration time and arbitration logic (per device) can be reduce by increasing bus width. Alternatively, this method allows the number of devices connected to a bus to be increased without changing the arbitration logic of each device (or the number of arbitration steps)., only the width of the arbitration bus must be increased in this case.
name of conference
Proceedings of 8th International Parallel Processing Symposium