EFFICIENT IMAGE COMPUTATIONS ON VLSI ARCHITECTURES WITH REDUCED HARDWARE.

The authors consider efficient parallel solutions to basic image processing problems on parallel architectures with reduced number of processors. The first proposed organization has n**2 memory modules to perform several image processing computations on an n multiplied by n image. This SIMD (single-instruction-multiple-data-stream) architecture has simple overall organization, low processing requirements, and can be implemented using a limited VLSI chip set or off-the-shelf components. Many image computations which can be performed in O(n) time on a mesh-connected computer (MCC) with n**2 PEs (processing elements), can also be performed in O(n) time on this structure with n PEs. The authors also show that the proposed architecture with n processors has superior performance to other proposed architectures that are based on a linear array of n processors, even if each processor in the linear array has enough memory to hold an entire row or column of the image. A class of reduced hardware organizations with nk processors and n**2 memory modules, where 1 less than equivalent to k less than equivalent to n, is introduced. It can perform many computations related to single figures in O(n/k plus k) time and provides linear speedup in the range 1 less than equivalent to k less than equivalent to n**1**/**2.

EFFICIENT IMAGE COMPUTATIONS ON VLSI ARCHITECTURES WITH REDUCED HARDWARE. Conference Paper