Routing BPC permutations in VLSI Conference Paper

abstract

• A large number of the permutations realized by interconnection networks in parallel processing systems and digital arithmetic circuits, fall in the class of bit-permute-complement (BPC) permutations. This paper presents a methodology for routing this class of permutations in VLSI, under various I/O, area, and time trade-offs. The resulting VLSI designs can route a BPC permutation of size N, using a chip with N/Q I/O pins, O(N2/Q2) area, and O(wQ) time, where w is the word length of the permuted elements and 1QN/w.

name of conference

• Proceedings Sixth International Parallel Processing Symposium

authors

• Alnuweiri, Hussein

published proceedings

• Proceedings Sixth International Parallel Processing Symposium

author list (cited authors)

• Alnuweiri, H. M.

citation count

• 8

complete list of authors

• Alnuweiri, HM

publication date

• January 1992

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• Proceedings of the International Conference on Parallel Processing  Journal

Digital Object Identifier (DOI)

• 10.1109/ipps.1992.223061

International Standard Book Number (ISBN) 10

• 0818626720

start page

• 116

end page

• 119

URL

• http://dx.doi.org/10.1109/ipps.1992.223061