Multipriority packet switching on the HYPER switch
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This paper develops an efficient buffer management scheme that makes generic ATM switches capable of supporting delay-sensitive as well as loss-sensitive traffic. The proposed scheme aims at enhancing the performance of ATM switches by maintaining the head cells of output queues in relatively short dedicated output buffers, while maintaining the long tails of overflowing queues in a shared-memory pool where various memory-space management schemes can be applied. Under this scheme, delay-sensitive (high-priority) cells can be forwarded immediately to the output buffers, where priority-based cell scheduling is exercised. Loss-sensitive (low-priority) cells are pushed into the shared-memory only if their output buffers are full. If the shared memory is full, then a suitable push-out scheme must be employed to provide fairness. We investigate he impact of various buffer management and cell scheduling policies on the dynamics of interaction among the two traffic classes. The results demonstrate the effectiveness of the proposed scheme in providing each traffic class with the required quality-of-service (QoS) performance over a wide range of traffic loads and buffer sizes.
ATM 2000 Proceedings of the IEEE Conference on High Performance Switching and Routing (Cat No00TH8485)
author list (cited authors)
Alnuweiri, H. M., He, Y., & Ito, M.
complete list of authors
Alnuweiri, HM||He, Yue||Ito, Mabo