A FAST VLSI CHIP FOR COMPUTING THE 2-DIMENSIONAL DISCRETE COSINE TRANSFORM Conference Paper uri icon

abstract

  • A VLSI chip which performs an 8-point Discrete Cosine Transform using Distributed Arithmetic and Li's algorithm has been successfully designed and tested. Its total throughput is as high as 250 Mbits per second, which is of the order required for real-time applications such as the compression of video. Both the size and performance of the chip can be substantially improved through changes in its technology and design. Work on a 2-D DCT processor based on this unit is in progress.

name of conference

  • Proceedings of IEEE Pacific Rim Conference on Communications Computers and Signal Processing

published proceedings

  • IEEE PACIFIC RIM CONFERENCE ON COMMUNICATIONS, COMPUTERS AND SIGNAL PROCESSING : PROCEEDINGS, VOLS 1 AND 2

author list (cited authors)

  • WONG, W. S., BERNO, A., & ALNUWEIRI, H. M.

citation count

  • 1

complete list of authors

  • WONG, WS||BERNO, A||ALNUWEIRI, HM

publication date

  • January 1993