A Ladder Transistor-Clamped Multilevel Inverter with High-Voltage Variation Conference Paper

abstract

• 2017 IEEE. In this paper, a new ladder transistor clamped multilevel inverter topology is proposed with the aim of reducing the number of transistor, while maintaining the bidirectionalcontrolled current flow capability of the transistor-clamped topologies. The basic structural features of the topology are presented along with their operational purpose. The merits of the new topology with respect to other topologies in the low-voltage and high-voltage operations are discussed. In addition, the semimodular characteristics of the structure are discussed in regard to the scalability of the topology. Finally, the validity of the structure is demonstrated using simulation results for different voltage variations of the topology and a three-phase structure.

name of conference

• 2017 IEEE Energy Conversion Congress and Exposition (ECCE)

authors

• Abu-Rub, Haitham

published proceedings

• 2017 IEEE ENERGY CONVERSION CONGRESS AND EXPOSITION (ECCE)

author list (cited authors)

• Wodajo, E. T., Elbuluk, M., Choi, S., & Abu Rub, H.

citation count

• 2

complete list of authors

• Wodajo, Eshet T||Elbuluk, Malik||Choi, Seungdeog||Abu Rub, Haitham

publication date

• October 2017

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• n2329-3721ISSN  Journal

keywords

• High Voltage
• Ladder Topology
• Multilevel Inverter
• Scalability
• Transistor-clamped

Digital Object Identifier (DOI)

• 10.1109/ecce.2017.8096944

International Standard Book Number (ISBN) 13

• 9781509029983

start page

• 5679

end page

• 5684

volume

• 2017-January

URL

• http://dx.doi.org/10.1109/ecce.2017.8096944