A Ladder Transistor-Clamped Multilevel Inverter with High-Voltage Variation Conference Paper uri icon

abstract

  • © 2017 IEEE. In this paper, a new ladder transistor clamped multilevel inverter topology is proposed with the aim of reducing the number of transistor, while maintaining the bidirectionalcontrolled current flow capability of the transistor-clamped topologies. The basic structural features of the topology are presented along with their operational purpose. The merits of the new topology with respect to other topologies in the low-voltage and high-voltage operations are discussed. In addition, the semimodular characteristics of the structure are discussed in regard to the scalability of the topology. Finally, the validity of the structure is demonstrated using simulation results for different voltage variations of the topology and a three-phase structure.

author list (cited authors)

  • Wodaio, E. T., Elbuluk, M., Choi, S., & Abu Rub, H.

citation count

  • 1

publication date

  • October 2017

publisher