Fault tolerant permutation mapping in multistage interconnection network Academic Article

abstract

• An efficient scheme for fault tolerant mapping of permutations is designed. The proposed algorithm uses extra passes through the network, instead of additional hardware.

published proceedings

• Journal of Systems Architecture

author list (cited authors)

• Maulik, U., Bandyopadhyay, S., & Bhattacharyya, S.

citation count

• 1

complete list of authors

• Maulik, U||Bandyopadhyay, S||Bhattacharyya, S

publication date

• January 2000

publisher

• Elsevier  Publisher

published in

• Journal of Systems Architecture  Journal

Digital Object Identifier (DOI)

• 10.1016/s1383-7621(98)00078-2

start page

• 297

end page

• 300

volume

• 46

issue

• 3

URL

• http://dx.doi.org/10.1016/s1383-7621(98)00078-2