SC implementation of FIR filters for digital communication systems Conference Paper

abstract

• 1999 IEEE. In this paper a Switched-Capacitor (SC) architecture for the processing of binary input signals is presented. The architecture is especially useful for the realization of Finite Impulse Response (FIR) filters. A 23-th order Raised-Cosine (RC) filter employing 11 capacitors is designed. The filter has been simulated using a 0.8 m analog CMOS process. Hspice results have shown the feasibility of the proposed design technique.

name of conference

• Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303)

authors

• Silva-Martinez, Jose

published proceedings

• Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303)

author list (cited authors)

• Rocha-Perez, J. M., & Silva-Martinez, J.

citation count

• 3

complete list of authors

• Rocha-Perez, JM||Silva-Martinez, J

publication date

• January 1999

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

Digital Object Identifier (DOI)

• 10.1109/mmica.1999.833629

International Standard Book Number (ISBN) 10

• 0780355881

International Standard Book Number (ISBN) 13

• 9780780355880

start page

• 179

end page

• 182

URL

• http://dx.doi.org/10.1109/mmica.1999.833629