A 200MSPS Time-Interleaved 12-Bit ADC System with Digital Calibration Conference Paper uri icon


  • © 2017 IEEE. This paper proposes a time interleaved ADC architecture employing a digital background calibration technique based on evolutionary-computation. The algorithm iteratively minimizes an error function (EF) which models the gain, offset and timing mismatches between the ADC channels. The system was implemented using off-the-shelf Analog to Digital Converters (ADCs) and a Field Programmable Gate Array (FPGA). Experimental results demonstrate that the proposed calibration technique allows an SNDR improvement of 26dB for just 32 iterations of calibration.

author list (cited authors)

  • Bommireddipalli, A., Zhou, D., Talarico, C., Silva-Martinez, J., & Karsilayan, A. I.

citation count

  • 0

publication date

  • August 2017