Yield modeling for fault tolerant WSI arrays
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abstract
An approach to modeling the yield of WSI architectures in view of spatial distribution of defects on a wafer and varying clustering parameter is proposed. The results are mapped onto two-dimensional array architectures and the basis for determing the estimate for required redundancy of processing cells on various regions of the wafer has been proposed. The authors first elucidate the definitions of chip yield and wafer yield in VLSI and WSI to clarify the understanding of WSI wafer yield. The approach to modeling defect spatial distribution is discussed. A universal mesh interconnected processing cell array built on a wafer is analyzed using the model developed. The preliminary analysis is on a unit section and associated probability of a failure/failure-free composite section. This has been generalized in terms of spatial aspects of fault distribution to serve as a basis for the estimation of redundant cells for different sections of the array.
