A systolic array for image segmentation using split and merge procedure
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A systolic array architecture for image segmentation by a split and merge procedure is proposed. This architecture enhances the I/O and memory bandwidth requirements, which leads to speeding up the computation time of the segmentation of an image. The system structure is defined in terms of its interconnections and host computer interface along with other structural and behavioral considerations. Image segmentation through the proposed approach can be achieved in linear time.
Midwest Symposium on Circuits and Systems
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