Parallel implementation of a cut and paste maze routing algorithm Conference Paper uri icon

abstract

  • Wire routing has always been very compute bound phase in the realm of physical design of Very Large Integration Circuits (VLSI) circuits. Some of the software solutions to this problem entail divide and conquer methods like the hierarchical routing, etc., in order to reduce its time complexity. Recently, hardware accelerators have been employed to achieve further increase in the speed of this process. In this paper, implementation aspects of a reduced array architecture (RAA) for hardware acceleration of the cut and paste hierarchical routing algorithm are detailed. Several macros have been defined to implement the algorithm in hardware. The architecture has been implemented in double-metal 2ji CMOS technology.

author list (cited authors)

  • Kumar, H., Kalyan, R., Bayoumi, M., Tyagi, A., & Ling, N.

publication date

  • January 1993