Low Power Tiered Wake-up Module for Lightweight Embedded Systems using Cross Correlation
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A major objective in design of wearable and lig embedded systems is reducing the power consumption. Thi reduction of the battery size and enhances the wearabili system. In this paper, we propose an ultra low power tier up architecture with signal processing capability. The signal is based on template matching and normalized corss correla template matching at the beginning is performed with low sensit fewer bits and samples) but at very low power. Initial template removes signals that are obviously not of interest. If the signal i be of interest, the sensitivity and the power consumption of the matching blocks are gradually increased, until the signal of detected with a reasonable confidence. Consequently, a microco activated for additional processing. The tunable parameters for template matching include the number of samples, the size of template size) and the number of bits per sample. The proposed ar can enable the next generation of ultra low power or even b wearable and implantable computers due to tremendously the power consumption of the signal processing. We estimat power consumption of the proposed tiered wake-up circuitr three to six orders of magnitude smaller than state-of-the-art l microcontrollers, depending on the complexity of the template Further, the proposed architecture provides high level of progra which is lacking in ASIC architectures custom built for applic. 2011 IEEE.
name of conference
2011 International Conference on Body Sensor Networks
