Low-voltage low-overhead asynchronous logic
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A new delay-bounded asynchronous logic technique aimed at maximizing reliability at very low voltages is proposed. Compared to previous asynchronous logic approaches, the area and nominal delay overheads are small. Conventional standard cell libraries and conventional logic synthesis tools are used. The bounding delay elements used by the asynchronous controller feature programmable delays that are initially set based on static timing analysis. However, the delay elements are updated on-the-fly during actual operation of the circuit, resulting in strong resiliency even at low voltages and with extreme variations. Several benchmark circuits were implemented with the new asynchronous design flow using the 45nm TI process. Monte Carlo analysis demonstrates the expected resiliency. Compared to the equivalent synchronous circuits, the asynchronous versions have area overheads averaging 40%, although much smaller for large circuits. Nominal delay overheads average about 10%. 2013 IEEE.
name of conference
2013 IEEE International Symposium on Low Power Electronics and Design (ISLPED)
International Symposium on Low Power Electronics and Design (ISLPED)
author list (cited authors)
Sridharan, A., Sechen, C., & Jafari, R.
complete list of authors
Sridharan, Akshay||Sechen, Carl||Jafari, Roozbeh