A 13bit 200MS/s Pipeline ADC with Current-Mode MDACs Conference Paper uri icon

abstract

  • © 2017 IEEE. A 13bit 200MS/s pipeline ADC with current-mode MDAC is implemented in this work. Compared with a conventional MDAC architecture, the proposed current mode MDAC reduces power consumption for the residual amplifier between two pipelined stages. The fabricated ADC achieves a 58.4dB / 57.6dB SNDR and a 75dB / 72dB SFDR for a sinusoidal input at 4.15MHz / 97.9MHz respectively. The power consumption of the ADC operating at 200MS/s is 8.4mW and the conversion FoM is 64fJ/conv-step. The prototype occupies an active area of 0.23mm2 in a 40nm CMOS technology.

author list (cited authors)

  • Briseno-Vidrios, C., Zhou, D., Prakash, S., Liu, Q., Edward, A., & Silva-Martinez, J.

citation count

  • 3

publication date

  • May 2017

publisher