A 13bit 200MS/s Pipeline ADC with Current-Mode MDACs Conference Paper

abstract

• 2017 IEEE. A 13bit 200MS/s pipeline ADC with current-mode MDAC is implemented in this work. Compared with a conventional MDAC architecture, the proposed current mode MDAC reduces power consumption for the residual amplifier between two pipelined stages. The fabricated ADC achieves a 58.4dB / 57.6dB SNDR and a 75dB / 72dB SFDR for a sinusoidal input at 4.15MHz / 97.9MHz respectively. The power consumption of the ADC operating at 200MS/s is 8.4mW and the conversion FoM is 64fJ/conv-step. The prototype occupies an active area of 0.23mm2 in a 40nm CMOS technology.

name of conference

• 2017 IEEE International Symposium on Circuits and Systems (ISCAS)

authors

• Silva-Martinez, Jose

published proceedings

• 2017 IEEE International Symposium on Circuits and Systems (ISCAS)

author list (cited authors)

• Briseno-Vidrios, C., Zhou, D., Prakash, S., Liu, Q., Edward, A., & Silva-Martinez, J.

citation count

• 4

complete list of authors

• Briseno-Vidrios, Carlos||Zhou, Dadian||Prakash, Suraj||Liu, Qiyuan||Edward, Alexander||Silva-Martinez, Jose

publication date

• May 2017

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• IEEE International Symposium on Circuits and Systems  Journal

Digital Object Identifier (DOI)

• 10.1109/iscas.2017.8050690

International Standard Book Number (ISBN) 13

• 9781467368520

start page

• 1

end page

• 4

URL

• http://dx.doi.org/10.1109/iscas.2017.8050690