TESTING OF BIT-SERIAL MULTIPLIERS.
Conference Paper
Overview
Identity
Additional Document Info
View All
Overview
abstract
The problem of testing bit-serial processors is executed. Such processors have become an important element of many VLSI systems. Sequences of tests are derived for typical implementations of both fully bit-serial and bit-serial-parallel multipliers. The tests are based on comprehensive area-limited fault models. The problem for which this study provides a solution is a time-domain transformation of the difficult and generally unsolved problem of testing two-dimensional iterative logic arrays for multiple faults in the space domain.
