Co-Design of a High Performance 12-bit 8GHz DDR4 Switch on a Laminate-based CSP (Chip Scale Packaging) Technology Conference Paper

abstract

• 2016 IEEE. Multiplexer/switch ICs are key components of NVDIMM architecture that serve to isolate the host controller from the DRAM memory system. Signal integrity performance of the IC can drastically be impacted by package parasitics. In this paper we detailed a system co-design methodology that was employed to design a cost-effective DDR4 switch packaged in a laminate-based chip-scale packaging (CSP), without compromising electrical performance. The co-design simulation methodology is validated through correlation to laboratory measurements on TI's TS3DDR4000TM-a high performance 12-bit 8GHz DDR4 switch.

name of conference

• 2016 IEEE 66th Electronic Components and Technology Conference (ECTC)

authors

• Moreira-Tamayo, Oscar

published proceedings

• 2016 IEEE 66TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC)

author list (cited authors)

• Li, M., Moreira-Tamayo, O., & Murugan, R.

citation count

• 4

complete list of authors

• Li, Ming||Moreira-Tamayo, Oscar||Murugan, Rajen

publication date

• May 2016

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• Electronic Components and Technology Conference  Journal

keywords

• Co-design
• Csp
• Ddr4
• High-speed
• Nfbga

Digital Object Identifier (DOI)

• 10.1109/ECTC.2016.221

International Standard Book Number (ISBN) 13

• 9781509012039

start page

• 992

end page

• 996

volume

• 2016-August

URL

• http://dx.doi.org/10.1109/ectc.2016.221

user-defined tag

• 7 Affordable and Clean Energy