An FPGA-based transformable coprocessor for MPEG video processing Conference Paper uri icon

abstract

  • This paper demonstrates how an FPGA-based transformable coprocessor can be used to implement a real-time MPEG-1 video decoder with enhanced features. The transformable coprocessor consists of an FPGA, local static RAM, and a host bus interface built into the FPGA. The gate-limited FPGA core is reconfigured frequently to implement various parts of the video decoding process in real-time. Our results show that, through reconfiguration, FPGA-based processors can handle complex tasks (such as high-quality video decoding) adequately. We also identify the major bottlenecks that impede achieving higher speedups with the FPGAs. For MPEG-1 video processing, the major slowdown is caused by the excessive data transfers and bottlenecks due to bus interfaces and lack of sufficient storage in FPGA.

name of conference

  • High-Speed Computing, Digital Signal Processing, and Filtering Using Reconfigurable Logic

published proceedings

  • HIGH-SPEED COMPUTING, DIGITAL SIGNAL PROCESSING, AND FILTERING USING RECONFIGURABLE LOGIC

author list (cited authors)

  • Chow, H. A., & Alnuweiri, H.

citation count

  • 2

complete list of authors

  • Chow, HA||Alnuweiri, H

editor list (cited editors)

  • Schewel, J., Athanas, P. M., Bove, Jr., V. M., & Watson, J.

publication date

  • October 1996