A high precision closeloop programmable CMOS delay generator for UWB and time domain RF applications

This article presents a novel programmable high precision delay generator with adjustable digital control for ultra-wideband and time-domain RF applications.Ring oscillator based phase locked loop (PLL) is embedded to achieve desired propagation delay in the delay cell against process, temperature, and power supply variations. A replica inverter delay line parallel to the PLL offers a separate delay path for input clock. Sub-nanosecond delay step with high accuracy can be obtained by shaping the input clock slope and keeping a careful matching between the replica delay line and the delay cell in PLL. The prototype of the delay generator is implemented on a 0.18-m CMOS process. The measurement results show relative delay error of 0.8%. The circuit consumes 9.5 mA from a 1.8-V power supply. 2010 Wiley Periodicals, Inc.

A high precision closeloop programmable CMOS delay generator for UWB and time domain RF applications Academic Article