FAULT TOLERANCE TECHNIQUES FOR SYSTOLIC ARRAYS

abstract

• This article describes various techniques for fault tolerance that can be applied to systolic array architectures. The approach of algorithm-based fault tolerance is shown to be the natural one for such systems. Copyright 1987 by The Institute of Electrical and Electronics Engineers, Inc.

authors

• Reddy, Narasimha

published proceedings

• COMPUTER

author list (cited authors)

• ABRAHAM, J. A., BANERJEE, P., CHEN, C. Y., FUCHS, W. K., KUO, S. Y., & REDDY, A.

citation count

• 80

complete list of authors

• ABRAHAM, JA||BANERJEE, P||CHEN, CY||FUCHS, WK||KUO, SY||REDDY, ALN

publication date

• July 1987

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• Computer  Journal

Digital Object Identifier (DOI)

• 10.1109/mc.1987.1663621

start page

• 65

end page

• 75

volume

• 20

issue

• 7

URL

• http://dx.doi.org/10.1109/mc.1987.1663621