6.8mW 2.5Gb/s and 42.5mW 5Gb/s 1:8 CMOS demultiplexers Conference Paper

abstract

• This paper presents two low-power demultiplexers working at 2.5Gbps and 5Gbps input data rate respectively. The 2.5Gbps demultiplexer consumes only 6.8mW power dissipation. The 5Gbps demultiplexer consumes 42.5mW power dissipation. The two demultiplexers are implemented in TSMC 0.35 m CMOS technology. They are built on the same chip sharing input and output ports. The power supply of the chip is 2.5V. The demultiplexers are designed to be modules for optical communication receiver system.

authors

• Silva-Martinez, Jose

published proceedings

• Proceedings - IEEE International Symposium on Circuits and Systems

author list (cited authors)

• Cheng, S., & Silva-Martinez, J.

complete list of authors

• Cheng, S||Silva-Martinez, J

publication date

• September 2004

published in

• IEEE International Symposium on Circuits and Systems  Journal

volume

• 4