Adjustable CMOS voltage limiters for low-voltage applications
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This paper deals with the design of CMOS voltage limiters. The proposed topologies are based on the sample and held principle; wherein the circuits are driven by the comparison of the input signal and a control voltage. The voltage comparison is carried out by using complementary differential pairs for single ended structures or two parallel connected transistors if balanced inputs are available. The resulting topologies are efficient and simple.
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