Low-Power Fully Integrated CMOS DTV Tuner Front-End for ATSC Terrestrial Broadcasting Academic Article uri icon


  • A low-cost low-power DTV tuner for current digital television application is described. In order to increase integration level and reduce power consumption for off-air DTV tuner application, an SAW-filterless tuner front-end architecture is adopted. As a part of the concept, key building blocks for this architecture are implemented on a main stream 0.35 m CMOS technology. Experimental measurements for the prototype chip validate the system architecture; the prototype consumes 300 mw and achieves 45 dB of image rejection ratio within the entire 750 MHz frequency band.

published proceedings

  • VLSI Design

altmetric score

  • 3

author list (cited authors)

  • Xiao, J., Zhang, G., Li, T., & Silva-Martinez, J.

citation count

  • 4

complete list of authors

  • Xiao, Jianhong||Zhang, Guang||Li, Tianwei||Silva-Martinez, Jose

publication date

  • March 2007