A CMOS 1Gb/s 5-Tap Transversal Equalizer Based on Inductorless 3rd-Order Delay Cells Conference Paper

abstract

• The 5-tap FIR structure uses 3rd-order linear-phase cells to implement delays of 500ps for a T/2 fractionally-spaced equalizer. To improve the bandwidth of the summing circuit, the design incorporates a transimpedance load, increasing the bandwidth by a factor of 3.6 over a conventional resistive load. The equalizer consumes 96mW with 1.5V and occupies 0.26mm 2 in a CMOS 0.35m process. 2007 IEEE.

name of conference

• 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

authors

• Silva-Martinez, Jose

published proceedings

• 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

author list (cited authors)

• Hernandez-Garduno, D., & Silva-Martinez, J.

citation count

• 9

complete list of authors

• Hernandez-Garduno, David||Silva-Martinez, Jose

publication date

• February 2007

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• Digest of technical papers / IEEE International Solid-State Circuits Conference. IEEE International Solid-State Circuits Conference  Journal

Digital Object Identifier (DOI)

• 10.1109/isscc.2007.373379

International Standard Book Number (ISBN) 10

• 1424408539

International Standard Book Number (ISBN) 13

• 9781424408535

start page

• 232

end page

• 234

URL

• http://dx.doi.org/10.1109/isscc.2007.373379