Very linear CMOS floating resistor
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A very linear CMOS floating resistor is introduced. The proposed topology takes advantage of the MOS transistor characteristics biased in the linear region. It is claimed that the resistor linearity can be improved by reducing the AC voltage swing in the transistor terminals, the drain and the source, and using the linear behaviour between the gate voltage and the drain current. Simulated results, even in the presence of large transistors mismatches, have shown that the total harmonic distortion (THD) is lower than 0.1% for applied voltages up to 2 V peak to peak, VPTP. Resistance values of 500 and a frequency response up to 10 MHz have been simulated in a typical 3m CMOS process. The supply voltages was only 2.5 V. 1990, The Institution of Electrical Engineers. All rights reserved.