Low-Power 3rd-Order Continuous-Time Low-Pass Sigma-Delta Analog-to-Digital Converter for Wideband Applications Conference Paper uri icon

abstract

  • This paper presents the design of a low-power 3 rdorder continuous-time (CT) low-pass (LP) sigma-delta () analog-to-digital converter (ADC) with 20MHz bandwidth. The bandwidth of the system is large enough to accommodate LTE and other wideband wireless network standards. A 3 rd-order filter with feed-forward compensation is proposed to achieve low-power consumption and low complexity. A 3-bit flash quantizer is utilized to provide fast data conversion rate. The current-steering digital-to-analog converter (DAC) helps directly inject the feedback signal without additional circuitries. In order to avoid overall performance degradation from current glitches, cross-coupled transistors are adopted for the current steering DAC. The proposed system achieves a peak SNDR of 65.9 dB with 20 MHz bandwidth, a SFDR of 74.8 dBc, and a dynamic range (DR) of 62 dB, while it consumes 32.65 mW from a 1.8 V supply. The entire circuit is designed in a 0.18 m CMOS technology and is driven by 500MHz sampling rate. 2012 IEEE.

name of conference

  • 2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)

published proceedings

  • 2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)

author list (cited authors)

  • Kim, K., & Silva-Martinez, J.

citation count

  • 3

complete list of authors

  • Kim, Kunmo||Silva-Martinez, Jose

publication date

  • August 2012