Blocker and Jitter Tolerant Wideband Modulators Conference Paper uri icon

abstract

  • Blocker and jitter sensitivity of continuous-time sigma-delta (CT-) converters is discussed. The interaction between blockers and clock jitter and its effect on the ADC resolution is also investigated. It is observed that out-of-band (OOB) blockers and clock jitter in the feedback DAC degrade the ADC resolution by convolving with the OOB quantization noise, thereby increasing the in-band noise floor. Some techniques on how to improve the blocker and jitter tolerance of CT- ADCs are outlined. It is verified that increased blocker tolerance relaxes the baseband channel filtering requirements in the signal path of a broadband receiver. By monitoring the internal signals of the ADC and dynamically controlling a front-end programmable gain amplifier, saturation and overload is avoided in the presence of strong interferers. The proposed blocker mitigation technique avoids changing the ADC internal loop parameters dynamically, resulting in fast settling time performance with moderate penalties in SNDR and circuit complexity. 2012 IEEE.

name of conference

  • 2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)

published proceedings

  • 2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)

author list (cited authors)

  • Silva-Martinez, J., Karilayan, A. I., & Geddada, H. M.

citation count

  • 2

complete list of authors

  • Silva-Martinez, Jose||Kar┼čilayan, Aydin Ilker||Geddada, Hemasundar Mohan

publication date

  • January 2012