Algorithmic ADC operating with a single reference voltage for PLL-based chemical sensing applications Academic Article uri icon

abstract

  • This paper deals with the design of an algorithmic switched-capacitor analog-to-digital converter (ADC), operating with a single reference voltage, a single-ended amplifier, a single-ended comparator, and presenting a small input capacitance. The ADC requires two clock phases per conversion bit and N clock cycles to resolve the N-bits. The ADC achieves a measured peak signal-to-noise-ratio (SNR) of 49.9 dB and a peak signal-to-noise-and- distortion-ratio (SNDR) of 46.7 dB at Pin = -6dBFS with a sampling rate of 0.25 MS/s. The measured differential-non-linearity and integral-non-linearity are within +0.6/-0.5 and +0.2/-0.5 LSB, respectively. The ADC power consumption is 300 W and it is implemented in 90 nm CMOS technology with a single power supply of 1.2 V. The ADC saves power at system-level by requiring only a single reference voltage. At system level, this solution is therefore not only robust but competitive as well. 2013 Springer Science+Business Media New York.

published proceedings

  • Analog Integrated Circuits and Signal Processing

author list (cited authors)

  • Larsson, A., Kulkarni, R., Silva-Martinez, J., & Solis, S.

citation count

  • 0

complete list of authors

  • Larsson, A||Kulkarni, R||Silva-Martinez, J||Solis, S

publication date

  • February 2014