A 360 fJ/conversion-step, 14-bit, 100 MS/s, digitally background calibrated pipelined ADC in 130-nm CMOS Academic Article uri icon

abstract

  • 2014, Springer Science+Business Media New York. This paper describes a 14-bit digitally background calibrated pipeline analog-to-digital converter (ADC) implemented in a mainstream 130-nm CMOS technology. The proposed calibration technique linearizes the digital output to correct for errors resulting from capacitor mismatch, finite amplifier gain, voltage reference errors and differential offsets. The software-based calibration technique requires quite modest digital resources and its estimated dynamic power is under 1% of the ADC power consumption. After calibration, the 14-bit ADC achieves a measured peak Signal-to-Noise-plus-Distortion-Ratio of 71.1dB at 100MS/s sampling rate. The worst-case integral nonlinearity is improved from 32.9 down to 4 Least-Significant-Bits after calibration. The chip occupies an active area of 1.25mm2 and the core ADC (S/H+analog+digital power) consumes 105mW. The Figure-of-Merit is 360fJ per conversion-step.

published proceedings

  • Analog Integrated Circuits and Signal Processing

author list (cited authors)

  • Larsson, A., Silva-Martinez, J., & Soenen, E. G.

citation count

  • 5

complete list of authors

  • Larsson, A||Silva-Martinez, J||Soenen, EG

publication date

  • October 2014