A 44.9% PAE Digitally-Assisted Linear Power Amplifier in 40 nm CMOS
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2014 IEEE. This paper presents a 1.9 GHz linear power amplifier (PA) architecture that improves its power efficiency in the power back-off (PBO) region. The combination of power transistor segmentation and digital gain compensation effectively enhances its power efficiency. A fast switching scheme is proposed, such that PA segments are switched on and off according to signal power, i.e. the proposed scheme makes the PA power consumption correlate with the power of the input signal. Binary power gain variations due to segmentation are dynamically compensated in the digital domain. The proposed solution overcomes the trade-off between efficiency and linearity by employing the digital predistortion technique. The PA is implemented in 40 nm CMOS process, it delivers a saturated output power of 35 dBm with 44.9% power-added efficiency (PAE) and linear gain of 38 dB. The adjacent channel leakage ratio (ACLR) at 5 MHz at a maximum linear output power of 31 dBm for a baseband WCDMA signal is -35.8 dBc.
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2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)
