A Digital-Circuit-Based Evolutionary-Computation Algorithm for Time-Interleaved ADC Background Calibration Conference Paper

abstract

• 2016 IEEE. Evolutionary computation, learning theory, neural networks, and fuzzy logic, are just few of the disciplines known as computational intelligence. In today's science and technology, computational intelligence techniques are widely used. They make use of computers' storage-and-speed abilities to address complex mathematical problems, which are difficult to be solved by conventional mathematical reasoning. In this paper, we introduce the design of a complex digital system implementing an evolutionary-computation algorithm to calibrate the mismatches affecting the performance of a time-interleaved Analog-to-Digital converter (TIADC). An error function (EF) is devised by modeling the three main issues limiting time-interleaved ADC performance: gain mismatches, offset mismatches and timing skews. The digital system is implemented on a Field-Programmable-Gate-Array (FPGA) and its digital logic and functionalities are tested by matching its simulation results against a Verilog-A behavioral model of the complete TIADC.

name of conference

• 2016 29th IEEE International System-on-Chip Conference (SOCC)

authors

• Silva-Martinez, Jose

published proceedings

• 2016 29th IEEE International System-on-Chip Conference (SOCC)

author list (cited authors)

• Zhou, D., Talarico, C., & Silva-Martinez, J.

citation count

• 9

complete list of authors

• Zhou, Dadian||Talarico, Claudio||Silva-Martinez, Jose

publication date

• January 2016

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• International System on Chip Conference  Journal

Digital Object Identifier (DOI)

• 10.1109/socc.2016.7905422

International Standard Book Number (ISBN) 13

• 9781509013661

start page

• 13

end page

• 17

URL

• http://dx.doi.org/10.1109/socc.2016.7905422