A very fast CMOS artificial cellular neural network Conference Paper uri icon

abstract

  • In this paper, techniques for the design of fast artificial cellular neural networks are presented. The speed limitations of the artificial Cellular Neural Networks (CNN's) are further discussed. As a result of this study an efficient and high speed CMOS architecture is proposed. In the implementation of the building blocks, very much attention is paid to speed, power consumption and silicon area. The convergence time of the network can easily be as short as 200 nano-seconds. The current consumption of a single neuron is less than 100 A, if all the templates are active. The network is internally re-configurable for noise reduction and edge detection. Simulated results for a 1010 network, consisting of 1700 transistors, configured to remove noise are reported. The supply voltages are only 0-3 volts.

name of conference

  • 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96

published proceedings

  • 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96

author list (cited authors)

  • Lobato-Lopez, F., Silva-Martinez, J., & Sanchez-Sinencio, E.

citation count

  • 1

complete list of authors

  • Lobato-Lopez, F||Silva-Martinez, J||Sanchez-Sinencio, E

publication date

  • January 1996

publisher