Supply regulation techniques for phase-locked loops Conference Paper

abstract

• Phase-locked loops (PLLs) which employ voltage regulators for low supply-noise sensitivity often rely upon significant decoupling capacitance to suppress negative (Gnd) supply noise and maintain low jitter. This paper compares various supply regulation techniques on the basis of their ability to reject noise from both positive and negative supplies. A novel replica-based dual-supply regulation technique is proposed which allows for significant reduction in decoupling capacitance for a given supply noise rejection. Comparison simulations in a 90nm CMOS technology show the replica-based dual-supply regulation technique achieving a worst case noise sensitivity of 1.6 rad/V, an improvement of 7.5 rad/V (15.1B) relative to a single-supply replica-based regulator topology. At 4.7GHz, the replica-based dual-supply regulated PLL consumes HmW from a 1.2V supply. 2009 IEEE.

name of conference

• 2009 IEEE Dallas Circuits and Systems Workshop (DCAS)

authors

• Palermo, Samuel

published proceedings

• 2009 IEEE Dallas Circuits and Systems Workshop (DCAS)

author list (cited authors)

• Gurumoorthy, V., & Palermo, S.

citation count

• 2

complete list of authors

• Gurumoorthy, Vivekananth||Palermo, Samuel

publication date

• January 2009

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

Digital Object Identifier (DOI)

• 10.1109/dcas.2009.5505764

International Standard Book Number (ISBN) 13

• 9781424454846

start page

• 1

end page

• 4

URL

• http://dx.doi.org/10.1109/dcas.2009.5505764