Power Efficiency Modeling and Optimization of High-Speed Equalized-Electrical I/O Architectures Conference Paper

abstract

• An I/O design framework is presented which combines statistical link analysis with circuit power models to predict the power-optimum equalization architecture, circuit style, and transmit swing at a given data rate, channel, and process node. 2010 IEEE.

name of conference

• 19th Topical Meeting on Electrical Performance of Electronic Packaging and Systems

authors

• Palermo, Samuel

published proceedings

• 19th Topical Meeting on Electrical Performance of Electronic Packaging and Systems

author list (cited authors)

• Palaniappan, A., & Palermo, S.

citation count

• 1

complete list of authors

• Palaniappan, Arun||Palermo, Samuel

publication date

• January 2010

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

Digital Object Identifier (DOI)

• 10.1109/epeps.2010.5642533

International Standard Book Number (ISBN) 13

• 9781424468652

start page

• 17

end page

• 20