Power Efficiency Modeling and Optimization of High-Speed Equalized-Electrical I/O Architectures Conference Paper uri icon

abstract

  • An I/O design framework is presented which combines statistical link analysis with circuit power models to predict the power-optimum equalization architecture, circuit style, and transmit swing at a given data rate, channel, and process node. 2010 IEEE.

name of conference

  • 19th Topical Meeting on Electrical Performance of Electronic Packaging and Systems

published proceedings

  • 19th Topical Meeting on Electrical Performance of Electronic Packaging and Systems

author list (cited authors)

  • Palaniappan, A., & Palermo, S.

citation count

  • 1

complete list of authors

  • Palaniappan, Arun||Palermo, Samuel

publication date

  • January 2010