CMOS Transceiver with Baud Rate Clock Recovery for Optical Interconnects Conference Paper

abstract

• An efficient baud rate clock and data recovery architecture is applied to a double sampling/integrating front-end receiver for optical interconnects. Receiver performance is analyzed and projected for future technologies. This front-end allows use of a 1:5 demux architecture to achieve 5Gb/s in a 0. 25m CMOS process. A 5:1 multiplexing transmitter is used to drive VCSELs for optical transmission. The transceiver chip consumes 145mW per link at 5Gb/s with a 2.5V supply.

name of conference

• 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525)

authors

• Palermo, Samuel

published proceedings

• 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525)

author list (cited authors)

• Emami-Neyestanak, A., Palermo, S., Lee, R., & Horowitz, M.

citation count

• 24

complete list of authors

• Emami-Neyestanak, Azita||Palermo, Samuel||Lee, Rae-Chang||Horowitz, Mark

publication date

• January 2004

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

keywords

• 40 Engineering
• 4008 Electrical Engineering

Digital Object Identifier (DOI)

• 10.1109/vlsic.2004.1346633

start page

• 410

end page

• 413

issue

• CIRCUITS SYMP.

URL

• http://dx.doi.org/10.1109/vlsic.2004.1346633