A 90nm CMOS 16Gb/s Transceiver for Optical Interconnects Conference Paper

abstract

• An optical interconnect transceiver incorporates a 4-tap FIR TX to reduce VCSEL average current and an integrating/double-sampling RX to eliminate the need for a bit-rate TIA. A dual-loop CDR with baud-rate phase detection further reduces power and area. Fabricated in a 1V 90nm CMOS process, the transceiver achieves 16Gb/s operation while consuming 129mW and occupying 0.105mm 2. 2007 IEEE.

name of conference

• 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

authors

• Palermo, Samuel

published proceedings

• 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

author list (cited authors)

• Palermo, S., Emami-Neyestanak, A., & Horowitz, M.

citation count

• 25

complete list of authors

• Palermo, Samuel||Emami-Neyestanak, Azita||Horowitz, Mark

publication date

• January 2007

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• Digest of technical papers / IEEE International Solid-State Circuits Conference. IEEE International Solid-State Circuits Conference  Journal

keywords

• 1 V
• 129 Mw
• 16 Gbit/s
• 90 Nm
• Bandwidth
• Baud-rate Phase Detection
• CMOS Integrated Circuits
• Clocks
• Cmos Process
• Integrated Optoelectronics
• Optical Feedback
• Optical Filters
• Optical Interconnect Transceiver
• Optical Interconnections
• Optical Receivers
• Optical Transmitters
• Phase Locked Loops
• Surface Emitting Lasers
• Transceivers
• Vcsel
• Vertical Cavity Surface Emitting Lasers

Digital Object Identifier (DOI)

• 10.1109/isscc.2007.373579

International Standard Book Number (ISBN) 10

• 1424408539

International Standard Book Number (ISBN) 13

• 9781424408535

start page

• 44

end page

• 46

URL

• http://dx.doi.org/10.1109/isscc.2007.373579