A 90nm CMOS 16Gb/s Transceiver for Optical Interconnects Conference Paper uri icon

abstract

  • An optical interconnect transceiver incorporates a 4-tap FIR TX to reduce VCSEL average current and an integrating/double-sampling RX to eliminate the need for a bit-rate TIA. A dual-loop CDR with baud-rate phase detection further reduces power and area. Fabricated in a 1V 90nm CMOS process, the transceiver achieves 16Gb/s operation while consuming 129mW and occupying 0.105mm 2. 2007 IEEE.

name of conference

  • 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

published proceedings

  • 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

author list (cited authors)

  • Palermo, S., Emami-Neyestanak, A., & Horowitz, M.

citation count

  • 25

complete list of authors

  • Palermo, Samuel||Emami-Neyestanak, Azita||Horowitz, Mark

publication date

  • January 2007