A 10 Gb/s 2-IIR-tap DFE receiver with 35 dB loss compensation in 65-nm CMOS

A serial I/O receiver efficiently implements a decision feedback equalizer (DFE) employing 2 IIR taps for improved long-tail ISI cancellation. The use of a modified multi-input two-stage slicer allows for both DFE summation to be performed directly at the slicer and optimization of the first-tap IIR filter/mux feedback path to allow for cancellation of the critical first post-cursor. Fabricated in GP 65-nm CMOS, the receiver occupies 0.0304 mm 2 area and consumes 9.9 mW while operating at a BER<10 -12 for 10 Gb/s data passed over a 40-inch FR4 channel with 35 dB loss at 5 GHz. 2013 JSAP.

A 10 Gb/s 2-IIR-tap DFE receiver with 35 dB loss compensation in 65-nm CMOS Conference Paper