Sub-10ps Resolution, Low Dead Time, Wide Range Two-Stage TDC A 15b

2014 IEEE. Advancements in imaging and ranging system performance creates the need for increased resolution, range, and speed of time-to-digital converters, a core part of the main data acquisition interface between the analog world and the ranging or imaging system's signal processing or computing core. In this paper, a coarse-fine hierarchical time-to-digital converter (TDC) utilizes two looped structures to achieve a wide dynamic range with high resolution and minimal dead time. The coarse stage consists of a looped TDC, a counter, and a novel counter clock control scheme which allows for indefinite range extension, while the fine stage employs a Vernier delay loop with a new edge-sensitive pulse-generator-based delay element that reduces loop non-linearity associated with mismatched rise/fall times. Also in order to achieve a high sampling rate and low dead-time during conversion, a control algorithm is devised and implemented at circuit level. Fabricated in 1.8V 0.18m CMOS, the TDC achieves an input range of 204.8ns, 8.125ps resolution, and 7.5ns dead-time, while utilizing 35mW at 100MS/s and 0.23mm2 in core area.

A 15b, Sub-10ps Resolution, Low Dead Time, Wide Range Two-Stage TDC Conference Paper