A 32 Gb/s 0.55 mW/Gbps PAM4 1-FIR 2-IIR Tap DFE Receiver in 65-nm CMOS

2015 JSAP. A PAM4 serial I/O receiver efficiently implements a decision feedback equalizer (DFE) that employs 1-FIR and 2-IIR taps for first post-cursor and long-tail ISI cancellation, respectively. The use of a single-clock phase two-stage regenerative comparator simplifies the quarter-rate receiver design and allows for sufficient gain to support PAM4 DFE. Optimization of the direct-feedback design's timing is achieved by cancelling the critical first post-cursor multi-level ISI directly at the comparator, while performing the remaining taps' ISI subtraction in a preceding current integration summer for improved sensitivity. Fabricated in GP 65-nm CMOS, the receiver occupies 0.0138 mm2 area and achieves power efficiencies of 0.55 and 0.52 mW/Gbps with 32 Gb/s and 25 Gb/s PAM4 data, respectively.

A 32 Gb/s 0.55 mW/Gbps PAM4 1-FIR 2-IIR Tap DFE Receiver in 65-nm CMOS Conference Paper